Attempts to increase the degree of integration of semiconductor devices on integrated circuit substrates have necessarily required a corresponding decrease in minimum dimensions and design rule tolerances. For example, with respect to field effect transistors, dimensions relating to lateral contact area, gate lengths and spacing have typically been reduced in order to achieve higher integration densities. However, because reductions in gate length and spacing may result in increased short channel effects and electrical shorting between contacts and active regions of a transistor, steps have been taken to prohibit these adverse consequences of device scaling. For example, to inhibit short-channel effects, shallow source/drain junctions have been used, as described in an article by M. Togo et al., entitled "Novel Deep Sub-Quarter Micron PMosfets With Ultra-Shallow Junctions Utilizing Boron Diffusion from Poly-Si/Oxide (BDSOX)", IEEE Symposium on VLSI Tech. Digest, pp. 21-22 (1994).
Unfortunately, such attempts may not adequately address the parasitics associated with increased contact resistance when misalignment of contacts becomes significant relative to the lateral dimensions of the transistor. For example, as illustrated by FIG. 1, misalignment between a conductive contact plug 20 and a source region 14 of a field effect transistor may cause the contact area between these two regions to be reduced significantly (as illustrated by region 21) and such reductions typically result in increases in parasitic contact resistance. Here, the transistor of FIG. 1 includes a substrate 10, source and drain regions 14 and an insulated gate electrode comprising a gate 12a, gate capping layer 12b and sidewall spacers 16. An electrically insulating interlayer 18 is also provided. Contact plugs are provided in contact holes formed within the interlayer 18.
Thus, notwithstanding attempts to provide field effect transistors having excellent electrical characteristics at reduced lateral dimensions, there continues to be a need for improved methods of forming field effect transistors and transistor formed thereby.